Recent advances in the miniaturization of integrated circuits have led to smaller chip areas available for devices. High density dynamic random access memory chips (DRAMs), for example, leave little room for the storage node of a memory cell. Yet, the storage node (capacitor) must be able to store a certain minimum charge, determined by design and operational parameters, to ensure reliable operation of the memory cell.
Operational problems arise when the DRAM capacitor capacitances fall below certain minimum thresholds. Firstly, the alpha-particle component of normal background radiation will generate hole-electron pairs in the silicon substrate plate of a cell capacitor. This phenomena will cause the charge within the affected cell capacitor to rapidly dissipate, resulting in a "soft" error. Secondly, as cell capacitance is decreased, the cell refresh time must generally be shortened, thus requiring more frequent interruptions for refresh overhead. Thus it is important for a DRAM designer to increase, or at least maintain, cell capacitance as cell size shrinks, without resorting to processes that reduce product yield or that markedly increase the number of masking and deposition steps in the production process.
Traditionally, capacitors integrated into memory cells have been patterned after the parallel plate capacitor. A dielectric material is deposited between the deposition of two conductive layers, which form the capacitor plates or electrodes. Several techniques have recently been developed to increase the total charge capacity of the cell capacitor without significantly affecting the chip area occupied by the cell. These include the use of new materials characterized by high dielectric constants, which permits much smaller interelectrode spacing.
Other techniques concentrate on increasing the effective surface area of the electrodes by creating folding structures such as trench or stacked capacitors. Such structures better utilize the available chip area by creating three dimensional shapes to which the conductive plates and interlayer dielectric conform. For example, U.S. Pat. No. 5,162,248 and U.S. Pat. No. 5,340,765, issued Aug. 23, 1994 to Dennison et al., both assigned to the assignee present invention, disclose related processes for forming capacitor structures resembling a cylindrical container. A polycrystalline silicon (polysilicon) container is first formed, both the inside and outside surfaces of which are available for use as the bottom electrode. More complex structures, such as the container-within-container structure disclosed in U.S. Pat. No. 5,340,763, issued Aug. 23, 1994 to Dennison, may further increase electrode surface area and allow the extension of conventional fabrication materials to future generation memory devices. The capacitor dielectric and top electrode may then be successively deposited.
The effective surface area of the plates may be even further increased by roughening the surface of the polysilicon layer. For example, rough layers may be formed by preferentially etching at grain boundaries of deposited polysilicon. Alternatively, hemispherical grained (HSG) silicon may be formed by gas phase nucleation or surface seeding. Among other processes, surface seeding may be accomplished by annealing a layer of amorphous silicon at a critical temperature and pressure, inducing surface migration of silicon atoms. Relatively large, hemispherical grains form by this redistribution, and the resultant HSG silicon layer provides a much larger electrode surface area than planar polysilicon.
Despite the greater electrode surface area provided by folding structures and roughened electrode surfaces, and partially because of these techniques, there remain limitations on capacitance of memory cells. The limited space over the access devices of dense circuits confines three dimensional folding stacked capacitors to a small volume. The capacitor dielectric must therefore be extremely thin to leave room for the top electrode. Furthermore, HSG silicon may grow upwards of 600 .ANG., occupying a great deal of the cell volume and further limiting the thickness of the capacitor dielectric. While dielectric thickness should be minimized in order to maximize capacitance, too thin a capacitor dielectric risks leakage current across the capacitor electrodes. Leakage current may result from pinholes in the dielectric and quantum tunneling effects, both of which phenomena are more likely to occur with thinner dielectrics. Thin capacitor dielectric layers are thus characterized by a low breakdown voltage, limiting the charge which may be stored on the bottom electrode before breakdown leakage occurs.
In addition, grains of HSG silicon may be so close together that dielectric bridging occurs between grains, creating thicker dielectric between grains than over grain surfaces. If the dielectric is deposited to the minimal thickness between HSG silicon grains, the dielectric over the grains will be too thin and lead to breakdown. Alternatively, when the dielectric is deposited to the minimal thickness over HSG silicon grains, the dielectric between the grains is too thick, leading to reduced capacitance.
The problems with thin dielectrics are exacerbated at corners of the cell electrodes. Standard manufacturing techniques, including planarization steps in the creation of stacked capacitors, result in a stacked capacitor structure with sharply angled edges. Higher charge densities naturally accumulate around angled corners, creating high electric field, or "edge effects." These high field effects further lower the breakdown voltage of the relatively thin dielectric layer, consequently reducing capacitance of the memory cell.
A need therefore exists for increasing the capacitance and reliability of an integrated memory cell capacitor. Preferably, such a capacitor and the process for its fabrication should be compatible with current integrated circuit fabrication techniques and structures in order to minimize the costs of implementation.